1. Field of the Invention
The present invention relates generally to semiconductor devices and a manufacturing method thereof. More particularly, the present invention relates to an arrangement of a semiconductor device including a polycrystalline silicon layer having an electrical connection portion wherein the silicon layer is connected with a conductive wiring layer and a method of manufacturing such device.
2. Description of the Background Art
Conventionally, for element isolation, a thick field oxide film is formed at a portion for isolating transistors, that is, at a field portion, of a MOS (Metal Oxide Semiconductor) type integrated circuit. As a method of forming such field oxide film, a generally-called LOCOS (Local Oxide of Silicon) method has been used in which a thermal oxide film is selectively formed at a part of a surface of a silicon substrate by making use of high acid-resistance of a silicon nitride film (Si.sub.3 N.sub.4 film). However, the LOCOS method prevents an increase of an integration density of a semiconductor device because of a generally-called bird's beak formed at a section of the film. In recent years, a method has come into use which utilizes a generally called field shield, in place of a field oxide film, as an element isolation means for use in LOCOS or the like. The field shield is directed t element isolation obtained by applying a bias voltage to a shield electrode comprising a conductive layer of polycrystalline silicon or the like and formed on a semiconductor substrate at a field portion, with a thin oxide film provided therebetween. This method enables element isolation at a field portion narrower than that in such a method utilizing a field oxide film as LOCOS method, thereby achieving higher integration density.
An arrangement and manufacturing processes of an element isolating region using a conventional field shield will be described in the following with reference to FIGS. 1A, 1B, and 2A through 2H.
FIGS. 1A and 1B show an example of an element isolation structure obtained by conventional field shield. With reference to these drawings, this element isolation structure obtained by the conventional field shield comprises a field shield electrode 3 including impurity doped polycrystalline silicon formed in thickness of about 2000.ANG. on a surface of a semiconductor substrate 1 formed of single crystalline p type silicon or the like, with an oxide film 2 about 500.ANG. thick provided therebetween by a CVD method or the like. The field shield electrode 3 is covered with an interlayer insulation film 4 about 2000.ANG. thick and a gate electrode 6 is patterned and formed on the surface of the interlayer insulation film 4. At an active region isolated and insulated by the shield electrode 3, the gate electrode is formed on the surface of the semiconductor substrate 1 with a gate insulation film 5 of several hundreds .ANG. in thickness provided therebetween. The gate electrode 6 and the other field shield electrode are covered with an interlayer insulation film 7. The interlayer insulation film 7 is provided with a contact hole 8 at a predetermined position, at which contact hole 8 a conductive wiring of aluminum or the like formed on the surface of the interlayer insulation film 7 and the field shield electrode 3 are electrically connected to each other. The conductive wiring layer 9 is provided for applying a bias voltage to the field shield electrode 3. With reference to FIG. 1B, formed at the opposite sides of the gate electrode 6 in the active region are impurity diffusion layers 10a and 10b of a conductivity type opposite to that of the semiconductor substrate 1, which layers serve as source/drain regions of an MOS field effect transistor. These impurity diffusion layers 10a and 10b are electrically connected to conductive wiring layers 12a and 12b of aluminum or the like at contact holes 11a and 11b, respectively.
Steps of manufacturing a semiconductor substrate having such arrangement wherein elements are isolated by conventional field shield will be described with reference to FIGS. 2A through 2H.
An impurity doped polycrystalline silicon layer 3 is deposited to about 2000.ANG. on the surface of a semiconductor substrate 1 by a CVD method, with an oxide film 2 about 200.ANG. thick formed by thermal oxidation or the like provided therebetween. Thereafter, an interlayer insulation film 4 about 2000.ANG. thick is deposited on the polycrystalline silicon layer 3 by the CVD method (FIG. 2A). Then, the interlayer insulation film 4, the polycrystalline silicon layer 3 and the oxide film 2 are sequentially and selectively etched by photolithography and etching to form a field shield portion (a portion indicated by arrow B in FIG. 2B), and the surface of the semiconductor substrate 1 at the active region surrounded by the field shield portion (a portion indicated by arrow C in FIG. 2B) is exposed. Thereafter, an oxide film of about 2000.ANG. in thickness is deposited over the surface of the semiconductor substrate 1 by the CVD method and then, a sidewall spacer 4a is formed around the field shield portion by anisotropic etching, resulting in the arrangement shown in FIG. 2B. Then, a gate oxide film 5 of about 500.ANG. in thickness is formed on the surface of the semiconductor substrate 1 in the active region by thermal oxidation and then, a polycrystalline silicon layer 6 with impurities such as phosphorus or arsenic doped therein is deposited all over the semiconductor substrate 1 by the CVD method or the like (FIG. 2C). During the thermal oxidation for forming the gate oxide film 5 which is carried out at a high temperature of about 820.degree. C. or above under an oxidizing atmosphere, oxides 13 are formed in several places of the polycrystalline silicon layer 3. The oxides 13 each have a diameter of about 2000.ANG. approximately the same as the grain diameter of the polycrystalline silicon. Since oxide 13 has a diameter of approximately 2000&lt;, providing a polycrystalline layer 3 thicker than 2000.ANG. prevents the formation of oxides 13 capable of extending completely through a thickness of polycrystalline layer 3. Therefore, to prevent formation of a leakage path through polycrystalline layer 3, a layer thickness of at least 2000.ANG. is required. Although the mechanism of formation of such oxide 13 is not definitely understood yet, the formation is thought to be caused by oxidation occurring along grain boundaries of the polycrystalline silicon layer 3 or by oxidation of the polycrystalline silicon grains themselves.
Then, the gate electrode 6 is patterned by photolithography and etching to result in the arrangement shown in FIG. 2D. Thereafter, an interlayer insulation film 7 is formed all over the semiconductor substrate 1 (FIG. 2E). A patterned resist film 14 is formed on the surface of the interlayer insulation film 7, which is used as a mask for anisotropic etching to form a contact hole 8. There would be no problem if such anisotropic etching enabled just a part of the interlayer insulation film 7, which part corresponds to a space serving as the contact hole 8, to be exactly and totally removed at the same time over the whole area of the part in order that the polycrystalline silicon layer 3 exposes its surface at the bottom of the contact hole 8. In practice, however, about 20% over etching is executed in consideration of variations in thickness of the interlayer insulation film 7, the variations resulted from a stepped substrate and variations in characteristic of the etching device. This over etching results in a removal of the oxide film 13 formed below the contact hole 8, thereby forming an opening portion 16 through the polycrystalline layer 3 and the oxide film 2, which opening includes the surface of the semiconductor substrate as a bottom portion (FIG. 2F).
Then, after a removal of the resist film 14, a conductive layer 9a of aluminum or the like is formed over the whole surface of the semiconductor substrate 1 including the inner wall of the contact hole 8 by the CVD method or sputtering (FIG. 2G). Thereafter, the conductive layer 9a is patterned by photolithography and etching to form conductive wiring layers 9, 12a and 12b (FIG. 2H).
The above-described conventional semiconductor device formed through such steps as described above has the following problems.
Since the opening portion 16 is also filled with aluminum at the time of forming the conductive wiring layers 9, 12a and 12b, the opening portion 16 functions as a leakage path causing current to leak between the conductive wiring layer 9 and the semiconductor substrate 1. The opening portion 16 serves as a leakage path when a total thickness of the oxide film 2 and the polycrystalline silicon layer 3 is less than about 20% of the thickness of the interlayer insulation film 4. The reason for this is as follows. That is, the interlayer insulation film 7 varies in thickness from place to place because of its stepped substrate. In addition, the etching devices themselves vary in characteristics such as an etching rate. However, in order to come into contact with the polycrystalline silicon layer 3, dry etching should be carried out to expose the polycrystalline silicon layer 3 at the thickest part of the interlayer insulation film 7. Thus, thinner part of the interlayer insulation film 7 is over etched, which is followed by etching of the oxide 13 at that time. When all the oxide 13 is etched as a result of this over etching, the conductive wiring layer 9 conducts with the semiconductor substrate 1 through the opening portion 16 to serve as a leakage path. Inferring from the variations in thickness of the interlayer insulation film 7 in practice, not all the oxide 13 is etched even at the thinnest part of the interlayer insulation film 4 as a result of over etching but some of it remains on the surface of the semiconductor substrate 1 when the total thickness of the oxide film 2 and the polycrystalline silicon layer 3 exceeds about 20% of the thickness of the interlayer insulation film 7. Therefore, no leakage path is generated. However, if the sum of the thicknesses of the oxide film 2 and the polycrystalline silicon layer 3 is equal to or less than about 20% of the thickness of the interlayer insulation film 7, all the oxide 13 is etched through over etching to generate a leakage path.
Such leakage path causes current to leak through the semiconductor substrate 1, thereby preventing an adequate application of a desired bias voltage to the polycrystalline layer 3 serving as a field shield electrode to deteriorate field characteristics of the field shield portion. Forming of a high acid-resistant nitride film by the CVD method on a surface of a formed oxide film 2 can be employed as a means for preventing a formation of an oxide film 13 in the polycrystalline layer 3 in the above-described conventional steps. However, an increase in the number of CVD steps lowers productivity, thereby preventing an improvement in mass production.